1. Field of the Invention
The present invention relates to a frequency synthesizer for use in a radar, a radio communication device, and so on.
2. Description of Related Art
Conventionally, frequency synthesizers disclosed in, for example, patent reference 1 and nonpatent reference 1 are known. FIG. 11 is a block diagram showing an example of a conventional frequency synthesizer as shown in patent reference 1. The frequency synthesizer shown in the figure is provided with a reference oscillator 101 for generating a reference signal, a clock signal, data signal, and load enable signal generating circuit 102 for generating a clock signal, a data signal, and a load enable signal which are to be inputted to a shift register circuit 103, the shift register circuit 103 for outputting PLL setting data on the basis of the data signal, a fractional modulator 104 for generating dividing number control data, and a fractional PLL synthesizer 105 for generating a high frequency signal.
The clock signal, data signal, and load enable signal generating circuit 102 generate a clock signal (CLK), a data signal (DATA), and a load enable signal (LE). The clock signal, the data signal, and the load enable signal are typically signals having lower speeds than that of the reference signal.
The shift register circuit 103 captures the data signal having PLL setting information on a rising edge of the clock signal into a register thereof, and performs a process associated with the descriptions of the data in the register and outputs PLL setting data on a rising edge of the load enable signal.
The fractional modulator 104 generates dividing number control data according to the PLL setting data outputted from the shift register circuit 103. The fractional PLL synthesizer 105 generates a high frequency signal according to both the reference signal generated by the reference oscillator 101 and the dividing number control data generated by the fractional modulator 104.
Further, FIG. 12 is a block diagram showing an example of a conventional frequency synthesizer, as described in nonpatent reference 1, which performs a parallel operation. The frequency synthesizer shown in FIG. 12 includes a reference oscillator 201 for generating a reference signal, a frequency setting data generating circuit 202 for generating frequency setting data for the frequency synthesizer, a phase difference setting data generating circuit 203 for generating phase difference setting data for the frequency synthesizer, a control circuit 204 for generating dividing number control data, and fractional PLL synthesizers 205 and 206 each for generating a high frequency signal. The control circuit 204 is comprised of a reset signal control circuit 207 for generating a reset signal at a time according to the phase difference setting data, and fractional modulators 208 and 209 each for generating dividing number control data.
The control circuit 204 generates dividing number control data according to the frequency setting data and the phase difference setting data in synchronization with the reference signal generated by the reference oscillator 201. The dividing number control data are generated by the fractional modulators 208 and 209 after a reset signal generated by a reset signal control circuit 207 is inputted to the fractional modulators. The fractional PLL synthesizer 205 generates a high frequency signal according to the reference signal generated by the reference oscillator 201 and the dividing number control data outputted from the fractional modulator 208. Similarly, the fractional PLL synthesizer 206 generates a high frequency signal according to the reference signal generated by the reference oscillator 201 and the dividing number control data outputted from the fractional modulator 209. At this time, because the same frequency setting data is provided for the fractional modulators 208 and 209, the frequencies of the high frequency signals of the fractional PLL synthesizers 205 and 206 are the same as each other.
The dividing number control data has periodicity. When the per period average of a dividing number is expressed as Nave, the frequency f0 of the output of each of the fractional PLL synthesizers is given by the following equation.
                              f          0                =                                            f              r                        ·                          N              ave                                =                                    f              r                        ·                          (                                                N                  0                                +                                  K                  M                                            )                                                          (        1        )            where fr is the frequency of the reference signal, N0 is the integer part of Nave, and K and M show the fractional part of Nave.
When phase synchronization is established in each of the fractional PLL synthesizers, the time difference between the rising edge of the reference signal whose period is fixed and the rising edge of the output signal of each of the fractional PLL synthesizers has a value depending on the dividing number control data. At this time, in the control circuit 204, the reset signal control circuit 207 outputs the reset signal to the fractional modulators 208 and 209 at a time according to the phase difference setting data. By initializing the operation of each of the modulators by using the reset signal, the frequency synthesizer carries out a cyclic shift on the dividing number control data to cause a phase difference occur between the high frequency signals generated by the fractional PLL synthesizers 205 and 206.
At this time, the phase difference Δθ between the high frequency signals generated by the fractional PLL synthesizers 205 and 206 for 1 of shift amount of the dividing number control data is given by the following equation.
                              Δ          ⁢                                          ⁢          θ                =                  2          ⁢                                          ⁢                      π            ·                          (                              K                M                            )                                                          (        2        )            As mentioned above, by initializing the operation of each of the modulators by using the reset signal according to the phase difference setting data, the frequency synthesizer carries out a cyclic shift on the dividing number control data to implement control of the phase difference between the high frequency signals generated by the fractional PLL synthesizers 205 and 206.